NVIDIA has announced nvqlink, a high-bandwidth, low-latency interconnect architecture designed to couple quantum processing units (QPUs) directly to GPU clusters. The announcement, made at NVIDIA's GTC 2026 conference, marks the company's most significant move yet into the quantum computing hardware ecosystem.

The nvqlink specification defines a coherent memory interface between QPUs and NVIDIA's Hopper-class and Blackwell-class GPUs, enabling hybrid quantum-classical workloads to pass data between quantum and classical processors without the overhead of traditional network I/O. NVIDIA claims the architecture reduces quantum-classical round-trip latency by up to 40× compared to existing PCIe-based approaches.

Why the Interconnect Matters

The bottleneck in hybrid quantum-classical computing has long been the interface between the two domains. Quantum processors excel at specific tasks — sampling from complex probability distributions, simulating quantum systems, solving certain optimisation problems — but require classical processors to handle pre- and post-processing, error mitigation, and algorithmic orchestration.

Existing approaches route data through standard network interfaces, introducing milliseconds of latency that are prohibitive for tight quantum-classical feedback loops. nvqlink addresses this by treating the QPU as a co-processor on the same memory fabric as the GPU, analogous to how NVLink connects GPU-to-GPU in NVIDIA's DGX systems.

"The quantum processor should feel like a native accelerator to the GPU, not a remote service. nvqlink makes that possible at the hardware level."
— Jensen Huang, CEO, NVIDIA

Compatible QPU Partners

NVIDIA has announced nvqlink compatibility agreements with three QPU manufacturers at launch: IonQ (trapped-ion), Quantinuum (trapped-ion), and QuEra Computing (neutral atom). IBM and Google are conspicuously absent from the initial partner list, though NVIDIA indicated the specification is open and additional partners are expected.

Each partner will implement an nvqlink-compatible interface card that slots into standard server chassis alongside NVIDIA GPUs, with a unified software stack based on NVIDIA's CUDA-Q framework. Developers write hybrid algorithms in Python or C++ using CUDA-Q APIs, and the runtime automatically dispatches quantum and classical sub-tasks to the appropriate processors.

Software Ecosystem: CUDA-Q

The hardware announcement is paired with a major update to CUDA-Q, NVIDIA's open-source platform for hybrid quantum-classical computing. CUDA-Q 2.0 introduces a unified programming model that abstracts over QPU backends, allowing developers to write once and target any nvqlink-compatible QPU.

The update also includes a new library of quantum kernels optimised for common hybrid workloads: variational quantum eigensolvers (VQE), quantum approximate optimisation algorithm (QAOA), and quantum machine learning circuits. These pre-built kernels are designed to run efficiently on current noisy intermediate-scale quantum (NISQ) hardware while remaining forward-compatible with fault-tolerant systems.

Market Implications

NVIDIA's entry into quantum interconnect hardware signals a significant shift in the competitive landscape. By positioning itself as the classical computing backbone for quantum systems, NVIDIA is betting that hybrid quantum-classical workloads — rather than standalone quantum computers — will define the near-term commercial quantum market.

Analysts at Quantum Computing Report estimate the hybrid quantum-classical systems market will reach $4.2 billion by 2028, with NVIDIA well-positioned to capture a substantial share through its existing GPU customer base and developer ecosystem.